Please use this identifier to cite or link to this item:
Type: Relatório
Title: A survey and taxonomy of layout compaction algorithms
Author(s)/Inventor(s): Anido, Manuel Lois
Oliveira, Carlo Emmanoel Tolla de
Abstract: This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential part of modern symbolic layout tools employed in VLSI circuit design. Layout compaction techniques are also used in the low-end stages of silicon compilation tools and module generators. The paper addresses the main algorithms used in compaction, focusing on their implementation characteristics, performance, advantages and drawbacks. Compaction is a highly important operation to optimize the use of silicon area, achieve higher speed through wire length minimization, support technology retargeting and also allow the use of legacy layouts. Optimized cells that were developed for a fabrication process with a set of design rules have to be retargeted for a new and more compact process with a different set of design rules.
Keywords: Compactação de algoritmos
Layout simbólico
VLSI (Integração em larga escala)
Compaction algorithms
Symbolic layout
EDA tools
CAD tools
Production unit: Instituto Tércio Pacitti de Aplicações e Pesquisas Computacionais
In: Relatório Técnico NCE
Issue: 1600
Issue Date: 30-Dec-2000
Publisher country: Brasil
Language: eng
Right access: Acesso Aberto
Citation: ANIDO, M. L.; OLIVEIRA, C. E. T. A survey and taxonomy of layout compaction algorithms. Rio de Janeiro: NCE/UFRJ, 2000. 25 p. (Relatório Técnico, 16/00)
Appears in Collections:Relatórios

Files in This Item:
File Description SizeFormat 
16_00_000612874.pdf1.74 MBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.