Please use this identifier to cite or link to this item: http://hdl.handle.net/11422/2589
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dc.contributor.authorPirmez, Luci-
dc.contributor.authorPedroza, A-
dc.contributor.authorMesquita, A-
dc.date.accessioned2017-08-04T12:45:08Z-
dc.date.available2017-08-06T03:00:16Z-
dc.date.issued1997-12-31-
dc.identifier.citationPIRMEZ, L.; PEDROZA, A.; MESQUITA, A. High level synthesis of protocols described by a formal description technique. Rio de Janeiro: NCE, UFRJ, 1997. 12 p. (Relatório Técnico, 04/97)pt_BR
dc.identifier.urihttp://hdl.handle.net/11422/2589-
dc.description.abstractA methodology that crriciently translates Estelle formal specifications into a VHDL description, suitab]c for High Levei Synthesis of communication protocols is proposed. The effect of the protocol description style in VHDL on the result of the HLS scheduling stcp is discussed by report to the Dynamic Loop Scheduling algorithm. An example using a test protocol is given.en
dc.languageengpt_BR
dc.relation.ispartofRelatório Técnico NCEpt_BR
dc.rightsAcesso Abertopt_BR
dc.subjectSíntese de alto nívelpt_BR
dc.subjectProtocolos de comunicaçãopt_BR
dc.subjectHigh-level synthesisen
dc.subjectCommunication protocolsen
dc.titleHigh level synthesis of protocols described by a formal description techniqueen
dc.typeRelatóriopt_BR
dc.publisher.countryBrasilpt_BR
dc.publisher.departmentInstituto Tércio Pacitti de Aplicações e Pesquisas Computacionaispt_BR
dc.subject.cnpqCNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAOpt_BR
dc.citation.issue0497pt_BR
dc.embargo.termsabertopt_BR
Appears in Collections:Relatórios Técnicos e de Pesquisa

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