Use este identificador para citar ou linkar para este item: http://hdl.handle.net/11422/2671
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dc.contributor.authorAude, Júlio Salek-
dc.contributor.authorMartins, F. R. S.-
dc.contributor.authorBarbosa, M. A. S.-
dc.contributor.authorJoão Junior, M.-
dc.contributor.authorYoung, M.T.-
dc.contributor.authorPinto, S. B.-
dc.date.accessioned2017-08-15T15:21:24Z-
dc.date.available2017-08-17T03:00:16Z-
dc.date.issued1999-12-31-
dc.identifier.citationAUDE, J. S. et al. NCESPARC+: an implementation of a SPARC architecture with hardware support to multithreading for the multiplus multiprocessor. Rio de Janeiro: NCE, UFRJ, 1999. 15 p. (Relatório Técnico, 27/99)pt_BR
dc.identifier.urihttp://hdl.handle.net/11422/2671-
dc.description.abstractNCESP ARC + is an implementation of the SP ARC v: 8 architecture with hardware support to a variable number of thread contexts, which is under development for use within the framework of the Multiplus distributed shared-memory multiprocessor. It is expected to provide an efficient and automatic mechanism to hide the latency of busy-waiting synchronization loops, cachecoherence protocol and remote memory access operations within the Multiplus multiprocessor. NCESPARC + performs context-switching in at most four processor cycles whenever there is an instruction cache miss, a data dependency in relation to the destination operand of a pending load instruction or a busy-waiting synchronization loop. It has a decoupled architecture which allows the main pipeline to process instructions from a given context while the Memory Interface Unit performs memory access operations related to that same context or to any other context. Results of simulation experiments show the impact of some architectural parameters on the NCESPARC + processor performance and demonstrate that the use of multiple thread contexts can e.ffectively produce a much better utilization of the processor when long latency operations are performed In addition, NCESPARC + processor performance with a single context is superior to that of a standard implementation of the SPARC architecture due to its decoupled architecture.en
dc.languageengpt_BR
dc.relation.ispartofRelatório Técnico NCEpt_BR
dc.rightsAcesso Abertopt_BR
dc.subjectMultithreadingpt_BR
dc.subjectMultiplus (Multiprocessador)pt_BR
dc.subjectSPARC architectureen
dc.titleNCESPARC+: an implementation of a SPARC architecture with hardware support to multithreading for the multiplus multiprocessoren
dc.typeRelatóriopt_BR
dc.publisher.countryBrasilpt_BR
dc.publisher.departmentInstituto Tércio Pacitti de Aplicações e Pesquisas Computacionaispt_BR
dc.subject.cnpqCNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAOpt_BR
dc.citation.issue2799pt_BR
dc.embargo.termsabertopt_BR
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