Unidade lógica e aritmética rápida de 32 bits

Abstract

This paper describes the analisys and LSI irnplementation of two 32-bit Arithmetic and Logic Unities. The main goal of this work is to evaluate the performance of the ALU; the one will be used as part of a RISC microprocessor based on the SPARC architecture, under development at NCE.\UFRJ within MULTIPLUS project. The circuit is being implemented in the Brazilian Multiproject using a 1,2μm CMOS ES2 technology. The full custom ALU layout has been designed using the Berkeley MAGIC V6 system and simulated using the IRSIM and SPICE tools running on a SUN IV workstation.